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Artigo de periodico
Experimental study of MISHEMT from 450 K down to 200 K for analog applications (2023)
Perina, Welder Fernandes; Martino, João Antonio ; Simoen, Eddy ; Peralagu, Uthayasankaran; Collaert, Nadine ; Agopian, Paula Ghedini Der
Source: Solid State Electronics. Unidade: EP
Subjects: TRANSISTORES, CIRCUITOS ANALÓGICOS, SEMICONDUTORES
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ABNT
PERINA, Welder Fernandes et al. Experimental study of MISHEMT from 450 K down to 200 K for analog applications. Solid State Electronics, v. 208, p. 1-4, 2023Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2023.108742. Acesso em: 07 maio 2024.
APA
Perina, W. F., Martino, J. A., Simoen, E., Peralagu, U., Collaert, N., & Agopian, P. G. D. (2023). Experimental study of MISHEMT from 450 K down to 200 K for analog applications. Solid State Electronics, 208, 1-4. doi:10.1016/j.sse.2023.108742
NLM
Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. Experimental study of MISHEMT from 450 K down to 200 K for analog applications [Internet]. Solid State Electronics. 2023 ; 208 1-4.[citado 2024 maio 07 ] Available from: https://doi.org/10.1016/j.sse.2023.108742
Vancouver
Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. Experimental study of MISHEMT from 450 K down to 200 K for analog applications [Internet]. Solid State Electronics. 2023 ; 208 1-4.[citado 2024 maio 07 ] Available from: https://doi.org/10.1016/j.sse.2023.108742
Trabalho de evento
Study of the effect of multiple conductions on threshold voltage in a MIS-HEMT from 450 K down to 200 K (2023)
Perina, Welder Fernandes; Martino, João Antonio ; Simoen, Eddy ; Peralagu, Uthayasankaran; Collaert, Nadine ; Agopian, Paula Ghedini Der
Source: SBMicro. Conference titles: Symposium on Microelectronics Technology and Devices. Unidade: EP
Subjects: TRANSISTORES, SEMICONDUTORES
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ABNT
PERINA, Welder Fernandes et al. Study of the effect of multiple conductions on threshold voltage in a MIS-HEMT from 450 K down to 200 K. 2023, Anais.. [Piscataway, N.J.]: IEEE, 2023. Disponível em: https://doi.org/10.1109/SBMicro60499.2023.10302604. Acesso em: 07 maio 2024.
APA
Perina, W. F., Martino, J. A., Simoen, E., Peralagu, U., Collaert, N., & Agopian, P. G. D. (2023). Study of the effect of multiple conductions on threshold voltage in a MIS-HEMT from 450 K down to 200 K. In SBMicro. [Piscataway, N.J.]: IEEE. doi:10.1109/SBMicro60499.2023.10302604
NLM
Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. Study of the effect of multiple conductions on threshold voltage in a MIS-HEMT from 450 K down to 200 K [Internet]. SBMicro. 2023 ;[citado 2024 maio 07 ] Available from: https://doi.org/10.1109/SBMicro60499.2023.10302604
Vancouver
Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. Study of the effect of multiple conductions on threshold voltage in a MIS-HEMT from 450 K down to 200 K [Internet]. SBMicro. 2023 ;[citado 2024 maio 07 ] Available from: https://doi.org/10.1109/SBMicro60499.2023.10302604
Trabalho de evento
Influence of gate insulator and AlGaN barrier layer on MISHEMT conduction mechanisms (2023)
Canales, Bruno Godoy; Martino, João Antonio ; Agopian, Paula Ghedini Der
Source: SBMicro. Conference titles: Symposium on Microelectronics Technology and Devices (SBMicro). Unidade: EP
Subjects: TRANSISTORES, SEMICONDUTORES
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ABNT
CANALES, Bruno Godoy e MARTINO, João Antonio e AGOPIAN, Paula Ghedini Der. Influence of gate insulator and AlGaN barrier layer on MISHEMT conduction mechanisms. 2023, Anais.. [Piscataway]: IEEE, 2023. Disponível em: https://doi.org/10.1109/SBMicro60499.2023.10302593. Acesso em: 07 maio 2024.
APA
Canales, B. G., Martino, J. A., & Agopian, P. G. D. (2023). Influence of gate insulator and AlGaN barrier layer on MISHEMT conduction mechanisms. In SBMicro. [Piscataway]: IEEE. doi:10.1109/SBMicro60499.2023.10302593
NLM
Canales BG, Martino JA, Agopian PGD. Influence of gate insulator and AlGaN barrier layer on MISHEMT conduction mechanisms [Internet]. SBMicro. 2023 ;[citado 2024 maio 07 ] Available from: https://doi.org/10.1109/SBMicro60499.2023.10302593
Vancouver
Canales BG, Martino JA, Agopian PGD. Influence of gate insulator and AlGaN barrier layer on MISHEMT conduction mechanisms [Internet]. SBMicro. 2023 ;[citado 2024 maio 07 ] Available from: https://doi.org/10.1109/SBMicro60499.2023.10302593
Artigo de periodico
MISHEMT intrinsic voltage gain under multiple channel output characteristics (2023)
Canales, Bruno Godoy; Perina, Welder Fernandes; Martino, João Antonio ; Simoen, Eddy ; Peralagu, Uthayasankaran; Collaert, Nadine ; Agopian, Paula Ghedini Der
Source: Semiconductor Science and Technology. Unidade: EP
Subjects: TRANSISTORES, SEMICONDUTORES
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ABNT
CANALES, Bruno Godoy et al. MISHEMT intrinsic voltage gain under multiple channel output characteristics. Semiconductor Science and Technology, v. 38, n. 11, p. 1-6, 2023Tradução . . Disponível em: https://doi.org/10.1088/1361-6641/acfa1f. Acesso em: 07 maio 2024.
APA
Canales, B. G., Perina, W. F., Martino, J. A., Simoen, E., Peralagu, U., Collaert, N., & Agopian, P. G. D. (2023). MISHEMT intrinsic voltage gain under multiple channel output characteristics. Semiconductor Science and Technology, 38( 11), 1-6. doi:10.1088/1361-6641/acfa1f
NLM
Canales BG, Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. MISHEMT intrinsic voltage gain under multiple channel output characteristics [Internet]. Semiconductor Science and Technology. 2023 ; 38( 11): 1-6.[citado 2024 maio 07 ] Available from: https://doi.org/10.1088/1361-6641/acfa1f
Vancouver
Canales BG, Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. MISHEMT intrinsic voltage gain under multiple channel output characteristics [Internet]. Semiconductor Science and Technology. 2023 ; 38( 11): 1-6.[citado 2024 maio 07 ] Available from: https://doi.org/10.1088/1361-6641/acfa1f
Trabalho de evento
Experimental behavior of line-TFET applied to low-dropout voltage regulator (2022)
Silva, Wenita de Lima; Agopian, Paula Ghedini Der ; Martino, João Antonio
Source: SBMICRO: proceedings. Conference titles: Symposium on Microelectronics Technology. Unidade: EP
Subjects: SEMICONDUTORES, ESTABILIDADE, CIRCUITOS ANALÓGICOS
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ABNT
SILVA, Wenita de Lima e AGOPIAN, Paula Ghedini Der e MARTINO, João Antonio. Experimental behavior of line-TFET applied to low-dropout voltage regulator. 2022, Anais.. [s.L.]: IEEE, 2022. Disponível em: https://doi.org/10.1109/SBMICRO55822.2022.9881041. Acesso em: 07 maio 2024.
APA
Silva, W. de L., Agopian, P. G. D., & Martino, J. A. (2022). Experimental behavior of line-TFET applied to low-dropout voltage regulator. In SBMICRO: proceedings. [s.L.]: IEEE. doi:10.1109/SBMICRO55822.2022.9881041
NLM
Silva W de L, Agopian PGD, Martino JA. Experimental behavior of line-TFET applied to low-dropout voltage regulator [Internet]. SBMICRO: proceedings. 2022 ;[citado 2024 maio 07 ] Available from: https://doi.org/10.1109/SBMICRO55822.2022.9881041
Vancouver
Silva W de L, Agopian PGD, Martino JA. Experimental behavior of line-TFET applied to low-dropout voltage regulator [Internet]. SBMICRO: proceedings. 2022 ;[citado 2024 maio 07 ] Available from: https://doi.org/10.1109/SBMICRO55822.2022.9881041
Artigo de periodico
Performance of differential pair circuits designed with line tunnel FET devices at different temperatures (2018)
Martino, Márcio Dalla Valle; Claeys, Cor ; Agopian, Paula Ghedini Der ; Rooyackers, Rita; Simoen, Eddy ; Martino, João Antonio
Source: Semiconductor Science and Technology. Unidade: EP
Assunto: SEMICONDUTORES
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ABNT
MARTINO, Márcio Dalla Valle et al. Performance of differential pair circuits designed with line tunnel FET devices at different temperatures. Semiconductor Science and Technology, v. 33, n. 7, p. 075012, 2018Tradução . . Disponível em: https://doi.org/10.1088/1361-6641/aac4fd. Acesso em: 07 maio 2024.
APA
Martino, M. D. V., Claeys, C., Agopian, P. G. D., Rooyackers, R., Simoen, E., & Martino, J. A. (2018). Performance of differential pair circuits designed with line tunnel FET devices at different temperatures. Semiconductor Science and Technology, 33( 7), 075012. doi:10.1088/1361-6641/aac4fd
NLM
Martino MDV, Claeys C, Agopian PGD, Rooyackers R, Simoen E, Martino JA. Performance of differential pair circuits designed with line tunnel FET devices at different temperatures [Internet]. Semiconductor Science and Technology. 2018 ; 33( 7): 075012.[citado 2024 maio 07 ] Available from: https://doi.org/10.1088/1361-6641/aac4fd
Vancouver
Martino MDV, Claeys C, Agopian PGD, Rooyackers R, Simoen E, Martino JA. Performance of differential pair circuits designed with line tunnel FET devices at different temperatures [Internet]. Semiconductor Science and Technology. 2018 ; 33( 7): 075012.[citado 2024 maio 07 ] Available from: https://doi.org/10.1088/1361-6641/aac4fd
Artigo de periodico
Analysis of proton irradiated n- and p-type strained FinFETs at low temperatures down to 100 K (2018)
Caparroz, Luís Felipe Vicentis; Agopian, Paula Ghedini Der ; Claeys, Cor ; Simoen, Eddy ; Bordallo, Caio Cesar Mendes ; Martino, João Antonio
Source: Semiconductor Science and Technology. Unidades: EP, EACH
Subjects: TEMPERATURA, SEMICONDUTORES
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ABNT
CAPARROZ, Luís Felipe Vicentis et al. Analysis of proton irradiated n- and p-type strained FinFETs at low temperatures down to 100 K. Semiconductor Science and Technology, v. 33, n. 6, p. 065003, 2018Tradução . . Disponível em: https://doi.org/10.1088/1361-6641/aabab3. Acesso em: 07 maio 2024.
APA
Caparroz, L. F. V., Agopian, P. G. D., Claeys, C., Simoen, E., Bordallo, C. C. M., & Martino, J. A. (2018). Analysis of proton irradiated n- and p-type strained FinFETs at low temperatures down to 100 K. Semiconductor Science and Technology, 33( 6), 065003. doi:10.1088/1361-6641/aabab3
NLM
Caparroz LFV, Agopian PGD, Claeys C, Simoen E, Bordallo CCM, Martino JA. Analysis of proton irradiated n- and p-type strained FinFETs at low temperatures down to 100 K [Internet]. Semiconductor Science and Technology. 2018 ; 33( 6): 065003.[citado 2024 maio 07 ] Available from: https://doi.org/10.1088/1361-6641/aabab3
Vancouver
Caparroz LFV, Agopian PGD, Claeys C, Simoen E, Bordallo CCM, Martino JA. Analysis of proton irradiated n- and p-type strained FinFETs at low temperatures down to 100 K [Internet]. Semiconductor Science and Technology. 2018 ; 33( 6): 065003.[citado 2024 maio 07 ] Available from: https://doi.org/10.1088/1361-6641/aabab3
Artigo de periodico
The impact of the temperature on In0.53Ga0.47As nTFETs (2018)
Bordallo, Caio Cesar Mendes ; Mocuta, Dan; Collaert, Nadine ; Alian, A; Simoen, Eddy ; Claeys, Cor ; Agopian, Paula Ghedini Der ; Martino, João Antonio ; Rooyackers, Rita; Mols, Yannick; Van Dooren, A; Verhulst, Anne S; Lin, D
Source: Composants nanoélectroniques. Unidade: EP
Assunto: SEMICONDUTORES
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ABNT
BORDALLO, Caio Cesar Mendes et al. The impact of the temperature on In0.53Ga0.47As nTFETs. Composants nanoélectroniques, v. 18, n. 1, 2018Tradução . . Disponível em: https://doi.org/10.21494/iste.op.2018.0224. Acesso em: 07 maio 2024.
APA
Bordallo, C. C. M., Mocuta, D., Collaert, N., Alian, A., Simoen, E., Claeys, C., et al. (2018). The impact of the temperature on In0.53Ga0.47As nTFETs. Composants nanoélectroniques, 18( 1). doi:10.21494/iste.op.2018.0224
NLM
Bordallo CCM, Mocuta D, Collaert N, Alian A, Simoen E, Claeys C, Agopian PGD, Martino JA, Rooyackers R, Mols Y, Van Dooren A, Verhulst AS, Lin D. The impact of the temperature on In0.53Ga0.47As nTFETs [Internet]. Composants nanoélectroniques. 2018 ;18( 1):[citado 2024 maio 07 ] Available from: https://doi.org/10.21494/iste.op.2018.0224
Vancouver
Bordallo CCM, Mocuta D, Collaert N, Alian A, Simoen E, Claeys C, Agopian PGD, Martino JA, Rooyackers R, Mols Y, Van Dooren A, Verhulst AS, Lin D. The impact of the temperature on In0.53Ga0.47As nTFETs [Internet]. Composants nanoélectroniques. 2018 ;18( 1):[citado 2024 maio 07 ] Available from: https://doi.org/10.21494/iste.op.2018.0224
Artigo de periodico
Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies (2017)
Itocazu, Vitor Tatsuo ; Sonnenberg, Victor ; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Source: Journal of Integrated Circuits and Systems. Unidade: EP
Assunto: SEMICONDUTORES
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ABNT
ITOCAZU, Vitor Tatsuo et al. Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies. Journal of Integrated Circuits and Systems, v. 12, n. 2, p. 82-88, 2017Tradução . . Disponível em: https://doi.org/10.29292/jics.v12i2.455. Acesso em: 07 maio 2024.
APA
Itocazu, V. T., Sonnenberg, V., Martino, J. A., Simoen, E., & Claeys, C. (2017). Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies. Journal of Integrated Circuits and Systems, 12( 2), 82-88. doi:10.29292/jics.v12i2.455
NLM
Itocazu VT, Sonnenberg V, Martino JA, Simoen E, Claeys C. Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies [Internet]. Journal of Integrated Circuits and Systems. 2017 ; 12( 2): 82-88.[citado 2024 maio 07 ] Available from: https://doi.org/10.29292/jics.v12i2.455
Vancouver
Itocazu VT, Sonnenberg V, Martino JA, Simoen E, Claeys C. Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies [Internet]. Journal of Integrated Circuits and Systems. 2017 ; 12( 2): 82-88.[citado 2024 maio 07 ] Available from: https://doi.org/10.29292/jics.v12i2.455
Artigo de periodico
Analysis of current mirror circuits designed with line tunnel FET devices at different temperatures (2017)
Martino, Márcio Dalla Valle; Claeys, Cor ; Rooyackers, Rita; Simoen, Eddy ; Agopian, Paula Ghedini Der ; Vandooren, A; Martino, João Antonio
Source: Semiconductor Science and Technology. Unidade: EP
Subjects: TRANSISTORES, SEMICONDUTORES
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ABNT
MARTINO, Márcio Dalla Valle et al. Analysis of current mirror circuits designed with line tunnel FET devices at different temperatures. Semiconductor Science and Technology, v. 32, n. 5, p. 055015, 2017Tradução . . Disponível em: https://doi.org/10.1088/1361-6641/aa6764. Acesso em: 07 maio 2024.
APA
Martino, M. D. V., Claeys, C., Rooyackers, R., Simoen, E., Agopian, P. G. D., Vandooren, A., & Martino, J. A. (2017). Analysis of current mirror circuits designed with line tunnel FET devices at different temperatures. Semiconductor Science and Technology, 32( 5), 055015. doi:10.1088/1361-6641/aa6764
NLM
Martino MDV, Claeys C, Rooyackers R, Simoen E, Agopian PGD, Vandooren A, Martino JA. Analysis of current mirror circuits designed with line tunnel FET devices at different temperatures [Internet]. Semiconductor Science and Technology. 2017 ; 32( 5): 055015.[citado 2024 maio 07 ] Available from: https://doi.org/10.1088/1361-6641/aa6764
Vancouver
Martino MDV, Claeys C, Rooyackers R, Simoen E, Agopian PGD, Vandooren A, Martino JA. Analysis of current mirror circuits designed with line tunnel FET devices at different temperatures [Internet]. Semiconductor Science and Technology. 2017 ; 32( 5): 055015.[citado 2024 maio 07 ] Available from: https://doi.org/10.1088/1361-6641/aa6764
Artigo de periodico
The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs (2017)
Bordallo, Caio Cesar Mendes ; Collaert, Nadine ; Claeys, Cor ; Simoen, Eddy ; Vandooren, A; Rooyackers, Rita; Mols, Yannick; Alian, A; Agopian, Paula Ghedini Der ; Martino, João Antonio
Source: IEEE Transactions on Electron Devices. Unidade: EP
Subjects: MICROELETRÔNICA, SEMICONDUTORES
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ABNT
BORDALLO, Caio Cesar Mendes et al. The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs. IEEE Transactions on Electron Devices, v. 64, n. 9, p. 3595-3600, 2017Tradução . . Disponível em: https://doi.org/10.1109/ted.2017.2721110. Acesso em: 07 maio 2024.
APA
Bordallo, C. C. M., Collaert, N., Claeys, C., Simoen, E., Vandooren, A., Rooyackers, R., et al. (2017). The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs. IEEE Transactions on Electron Devices, 64( 9), 3595-3600. doi:10.1109/ted.2017.2721110
NLM
Bordallo CCM, Collaert N, Claeys C, Simoen E, Vandooren A, Rooyackers R, Mols Y, Alian A, Agopian PGD, Martino JA. The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs [Internet]. IEEE Transactions on Electron Devices. 2017 ; 64( 9): 3595-3600.[citado 2024 maio 07 ] Available from: https://doi.org/10.1109/ted.2017.2721110
Vancouver
Bordallo CCM, Collaert N, Claeys C, Simoen E, Vandooren A, Rooyackers R, Mols Y, Alian A, Agopian PGD, Martino JA. The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs [Internet]. IEEE Transactions on Electron Devices. 2017 ; 64( 9): 3595-3600.[citado 2024 maio 07 ] Available from: https://doi.org/10.1109/ted.2017.2721110
Trabalho de evento-anais periodico
Study of line-TFET analog performance comparing with other TFET and MOSFET architectures (2017)
Agopian, Paula Ghedini Der ; Simoen, Eddy ; Vandooren, Anne; Rooyackers, Rita; Thean, Aaron; Claeys, Cor ; Martino, João Antonio
Source: Solid-State Electronics Volume 128, February 2017, Pages 43-47. Conference titles: EUROSOI-ULIS 2016. Unidade: EP
Assunto: SEMICONDUTORES
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ABNT
AGOPIAN, Paula Ghedini Der et al. Study of line-TFET analog performance comparing with other TFET and MOSFET architectures. Solid-State Electronics Volume 128, February 2017, Pages 43-47. [S.l.]: Escola Politécnica, Universidade de São Paulo. Disponível em: https://doi.org/10.1016/j.sse.2016.10.021. Acesso em: 07 maio 2024. , 2017
APA
Agopian, P. G. D., Simoen, E., Vandooren, A., Rooyackers, R., Thean, A., Claeys, C., & Martino, J. A. (2017). Study of line-TFET analog performance comparing with other TFET and MOSFET architectures. Solid-State Electronics Volume 128, February 2017, Pages 43-47. Escola Politécnica, Universidade de São Paulo. doi:10.1016/j.sse.2016.10.021
NLM
Agopian PGD, Simoen E, Vandooren A, Rooyackers R, Thean A, Claeys C, Martino JA. Study of line-TFET analog performance comparing with other TFET and MOSFET architectures [Internet]. Solid-State Electronics Volume 128, February 2017, Pages 43-47. 2017 ; 128 43-47.[citado 2024 maio 07 ] Available from: https://doi.org/10.1016/j.sse.2016.10.021
Vancouver
Agopian PGD, Simoen E, Vandooren A, Rooyackers R, Thean A, Claeys C, Martino JA. Study of line-TFET analog performance comparing with other TFET and MOSFET architectures [Internet]. Solid-State Electronics Volume 128, February 2017, Pages 43-47. 2017 ; 128 43-47.[citado 2024 maio 07 ] Available from: https://doi.org/10.1016/j.sse.2016.10.021
Artigo de periodico
Analog parameters of solid source Zn diffusion In X Ga1−X As nTFETs down to 10 K (2016)
Bordallo, Caio Cesar Mendes ; Vandooren, A; Rooyackers, Rita; Mols, Yannick; Alian, A; Agopian, Paula Ghedini Der ; Martino, João Antonio
Source: Semiconductor Science and Technology. Unidade: EP
Subjects: SEMICONDUTORES, MICROELETRÔNICA
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ABNT
BORDALLO, Caio Cesar Mendes et al. Analog parameters of solid source Zn diffusion In X Ga1−X As nTFETs down to 10 K. Semiconductor Science and Technology, v. 31, n. 12, p. 124001, 2016Tradução . . Disponível em: https://doi.org/10.1088/0268-1242/31/12/124001. Acesso em: 07 maio 2024.
APA
Bordallo, C. C. M., Vandooren, A., Rooyackers, R., Mols, Y., Alian, A., Agopian, P. G. D., & Martino, J. A. (2016). Analog parameters of solid source Zn diffusion In X Ga1−X As nTFETs down to 10 K. Semiconductor Science and Technology, 31( 12), 124001. doi:10.1088/0268-1242/31/12/124001
NLM
Bordallo CCM, Vandooren A, Rooyackers R, Mols Y, Alian A, Agopian PGD, Martino JA. Analog parameters of solid source Zn diffusion In X Ga1−X As nTFETs down to 10 K [Internet]. Semiconductor Science and Technology. 2016 ; 31( 12): 124001.[citado 2024 maio 07 ] Available from: https://doi.org/10.1088/0268-1242/31/12/124001
Vancouver
Bordallo CCM, Vandooren A, Rooyackers R, Mols Y, Alian A, Agopian PGD, Martino JA. Analog parameters of solid source Zn diffusion In X Ga1−X As nTFETs down to 10 K [Internet]. Semiconductor Science and Technology. 2016 ; 31( 12): 124001.[citado 2024 maio 07 ] Available from: https://doi.org/10.1088/0268-1242/31/12/124001
Artigo de periodico
Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature (2016)
Pavanello, Marcelo Antonio ; Souza, Michelly de; Ribeiro, Thales Augusto; Martino, João Antonio ; Flandre, Denis
Source: Semiconductor Science and Technology. Unidade: EP
Subjects: SILÍCIO, SEMICONDUTORES
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ABNT
PAVANELLO, Marcelo Antonio et al. Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature. Semiconductor Science and Technology, v. 31, n. 11, p. 114005, 2016Tradução . . Disponível em: https://doi.org/10.1088/0268-1242/31/11/114005. Acesso em: 07 maio 2024.
APA
Pavanello, M. A., Souza, M. de, Ribeiro, T. A., Martino, J. A., & Flandre, D. (2016). Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature. Semiconductor Science and Technology, 31( 11), 114005. doi:10.1088/0268-1242/31/11/114005
NLM
Pavanello MA, Souza M de, Ribeiro TA, Martino JA, Flandre D. Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature [Internet]. Semiconductor Science and Technology. 2016 ; 31( 11): 114005.[citado 2024 maio 07 ] Available from: https://doi.org/10.1088/0268-1242/31/11/114005
Vancouver
Pavanello MA, Souza M de, Ribeiro TA, Martino JA, Flandre D. Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature [Internet]. Semiconductor Science and Technology. 2016 ; 31( 11): 114005.[citado 2024 maio 07 ] Available from: https://doi.org/10.1088/0268-1242/31/11/114005
Artigo de periodico
Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes (2016)
Oliveira, Alberto Vinicius de; Agopian, Paula Ghedini Der ; Simoen, Eddy ; Langer, Robert; Collaert, Nadine ; Thean, Aaron; Claeys, Cor ; Martino, João Antonio
Source: Semiconductor Science and Technology. Unidade: EP
Subjects: SEMICONDUTORES, MICROELETRÔNICA
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ABNT
OLIVEIRA, Alberto Vinicius de et al. Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes. Semiconductor Science and Technology, v. 31, n. 11, p. 114002 , 2016Tradução . . Disponível em: https://doi.org/10.1088/0268-1242/31/11/114002. Acesso em: 07 maio 2024.
APA
Oliveira, A. V. de, Agopian, P. G. D., Simoen, E., Langer, R., Collaert, N., Thean, A., et al. (2016). Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes. Semiconductor Science and Technology, 31( 11), 114002 . doi:10.1088/0268-1242/31/11/114002
NLM
Oliveira AV de, Agopian PGD, Simoen E, Langer R, Collaert N, Thean A, Claeys C, Martino JA. Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes [Internet]. Semiconductor Science and Technology. 2016 ; 31( 11): 114002 .[citado 2024 maio 07 ] Available from: https://doi.org/10.1088/0268-1242/31/11/114002
Vancouver
Oliveira AV de, Agopian PGD, Simoen E, Langer R, Collaert N, Thean A, Claeys C, Martino JA. Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes [Internet]. Semiconductor Science and Technology. 2016 ; 31( 11): 114002 .[citado 2024 maio 07 ] Available from: https://doi.org/10.1088/0268-1242/31/11/114002
Artigo de periodico
Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation (2016)
Itocazu, Vitor Tatsuo ; Martino, João Antonio ; Sasaki, Kátia Regina Akemi; Simoen, Eddy ; Claeys, Cor ; Sonnenberg, Victor
Source: Journal of Integrated Circuits and Systems. Unidade: EP
Assunto: SEMICONDUTORES
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
ITOCAZU, Vitor Tatsuo et al. Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation. Journal of Integrated Circuits and Systems, v. 12, n. 2, p. 101-106, 2016Tradução . . Disponível em: https://doi.org/10.29292/jics.v12i2.458. Acesso em: 07 maio 2024.
APA
Itocazu, V. T., Martino, J. A., Sasaki, K. R. A., Simoen, E., Claeys, C., & Sonnenberg, V. (2016). Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation. Journal of Integrated Circuits and Systems, 12( 2), 101-106. doi:10.29292/jics.v12i2.458
NLM
Itocazu VT, Martino JA, Sasaki KRA, Simoen E, Claeys C, Sonnenberg V. Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation [Internet]. Journal of Integrated Circuits and Systems. 2016 ; 12( 2): 101-106.[citado 2024 maio 07 ] Available from: https://doi.org/10.29292/jics.v12i2.458
Vancouver
Itocazu VT, Martino JA, Sasaki KRA, Simoen E, Claeys C, Sonnenberg V. Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation [Internet]. Journal of Integrated Circuits and Systems. 2016 ; 12( 2): 101-106.[citado 2024 maio 07 ] Available from: https://doi.org/10.29292/jics.v12i2.458
Artigo de periodico
Low-Frequency Noise Analysis and Modeling in Vertical Tunnel FETs With Ge Source (2016)
Neves, Felipe S; Agopian, Paula Ghedini Der ; Cretu, B; Rooyackers, Rita; Vandooren, A; Simoen, Eddy ; Thean, Aaron; Martino, João Antonio
Source: IEEE Transactions on Electron Devices. Unidade: EP
Assunto: SEMICONDUTORES
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
NEVES, Felipe S et al. Low-Frequency Noise Analysis and Modeling in Vertical Tunnel FETs With Ge Source. IEEE Transactions on Electron Devices, v. 63, n. 4, p. 1658-1665, 2016Tradução . . Disponível em: https://doi.org/10.1109/ted.2016.2533360. Acesso em: 07 maio 2024.
APA
Neves, F. S., Agopian, P. G. D., Cretu, B., Rooyackers, R., Vandooren, A., Simoen, E., et al. (2016). Low-Frequency Noise Analysis and Modeling in Vertical Tunnel FETs With Ge Source. IEEE Transactions on Electron Devices, 63( 4), 1658-1665. doi:10.1109/ted.2016.2533360
NLM
Neves FS, Agopian PGD, Cretu B, Rooyackers R, Vandooren A, Simoen E, Thean A, Martino JA. Low-Frequency Noise Analysis and Modeling in Vertical Tunnel FETs With Ge Source [Internet]. IEEE Transactions on Electron Devices. 2016 ; 63( 4): 1658-1665.[citado 2024 maio 07 ] Available from: https://doi.org/10.1109/ted.2016.2533360
Vancouver
Neves FS, Agopian PGD, Cretu B, Rooyackers R, Vandooren A, Simoen E, Thean A, Martino JA. Low-Frequency Noise Analysis and Modeling in Vertical Tunnel FETs With Ge Source [Internet]. IEEE Transactions on Electron Devices. 2016 ; 63( 4): 1658-1665.[citado 2024 maio 07 ] Available from: https://doi.org/10.1109/ted.2016.2533360
Artigo de periodico
GR-Noise Characterization of Ge pFinFETs With STI First and STI Last Processes (2016)
Oliveira, Alberto Vinicius de; Simoen, Eddy ; Mitard, Jerome; Agopian, Paula Ghedini Der ; Langer, Robert; Witters, Liesbeth J; Martino, João Antonio
Source: IEEE Electron Device Letters. Unidade: EP
Subjects: SEMICONDUTORES, SILÍCIO
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
OLIVEIRA, Alberto Vinicius de et al. GR-Noise Characterization of Ge pFinFETs With STI First and STI Last Processes. IEEE Electron Device Letters, v. 37, n. 9, p. 1092-1095, 2016Tradução . . Disponível em: https://doi.org/10.1109/led.2016.2595398. Acesso em: 07 maio 2024.
APA
Oliveira, A. V. de, Simoen, E., Mitard, J., Agopian, P. G. D., Langer, R., Witters, L. J., & Martino, J. A. (2016). GR-Noise Characterization of Ge pFinFETs With STI First and STI Last Processes. IEEE Electron Device Letters, 37( 9), 1092-1095. doi:10.1109/led.2016.2595398
NLM
Oliveira AV de, Simoen E, Mitard J, Agopian PGD, Langer R, Witters LJ, Martino JA. GR-Noise Characterization of Ge pFinFETs With STI First and STI Last Processes [Internet]. IEEE Electron Device Letters. 2016 ; 37( 9): 1092-1095.[citado 2024 maio 07 ] Available from: https://doi.org/10.1109/led.2016.2595398
Vancouver
Oliveira AV de, Simoen E, Mitard J, Agopian PGD, Langer R, Witters LJ, Martino JA. GR-Noise Characterization of Ge pFinFETs With STI First and STI Last Processes [Internet]. IEEE Electron Device Letters. 2016 ; 37( 9): 1092-1095.[citado 2024 maio 07 ] Available from: https://doi.org/10.1109/led.2016.2595398
Artigo de periodico
Performance of TFET and FinFET devices applied to current mirrors for different dimensions and temperatures (2016)
Martino, Márcio Dalla Valle; Martino, João Antonio ; Agopian, Paula Ghedini Der ; Vandooren, A; Rooyackers, Rita; Simoen, Eddy ; Claeys, Cor
Source: Semiconductor Science and Technology. Unidade: EP
Assunto: SEMICONDUTORES
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
MARTINO, Márcio Dalla Valle et al. Performance of TFET and FinFET devices applied to current mirrors for different dimensions and temperatures. Semiconductor Science and Technology, v. 31, n. 5, 2016Tradução . . Disponível em: https://doi.org/10.1088/0268-1242/31/5/055001. Acesso em: 07 maio 2024.
APA
Martino, M. D. V., Martino, J. A., Agopian, P. G. D., Vandooren, A., Rooyackers, R., Simoen, E., & Claeys, C. (2016). Performance of TFET and FinFET devices applied to current mirrors for different dimensions and temperatures. Semiconductor Science and Technology, 31( 5). doi:10.1088/0268-1242/31/5/055001
NLM
Martino MDV, Martino JA, Agopian PGD, Vandooren A, Rooyackers R, Simoen E, Claeys C. Performance of TFET and FinFET devices applied to current mirrors for different dimensions and temperatures [Internet]. Semiconductor Science and Technology. 2016 ; 31( 5):[citado 2024 maio 07 ] Available from: https://doi.org/10.1088/0268-1242/31/5/055001
Vancouver
Martino MDV, Martino JA, Agopian PGD, Vandooren A, Rooyackers R, Simoen E, Claeys C. Performance of TFET and FinFET devices applied to current mirrors for different dimensions and temperatures [Internet]. Semiconductor Science and Technology. 2016 ; 31( 5):[citado 2024 maio 07 ] Available from: https://doi.org/10.1088/0268-1242/31/5/055001
Artigo de periodico
Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures (2016)
Oliveira, Alberto Vinicius de; Collaert, Nadine ; Thean, Aaron; Claeys, Cor ; Simoen, Eddy ; Agopian, Paula Ghedini Der ; Martino, João Antonio
Source: Solid-State Electronics. Unidade: EP
Subjects: SEMICONDUTORES, MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
OLIVEIRA, Alberto Vinicius de et al. Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures. Solid-State Electronics, v. 123, p. 124-129, 2016Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2016.05.004. Acesso em: 07 maio 2024.
APA
Oliveira, A. V. de, Collaert, N., Thean, A., Claeys, C., Simoen, E., Agopian, P. G. D., & Martino, J. A. (2016). Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures. Solid-State Electronics, 123, 124-129. doi:10.1016/j.sse.2016.05.004
NLM
Oliveira AV de, Collaert N, Thean A, Claeys C, Simoen E, Agopian PGD, Martino JA. Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures [Internet]. Solid-State Electronics. 2016 ; 123 124-129.[citado 2024 maio 07 ] Available from: https://doi.org/10.1016/j.sse.2016.05.004
Vancouver
Oliveira AV de, Collaert N, Thean A, Claeys C, Simoen E, Agopian PGD, Martino JA. Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures [Internet]. Solid-State Electronics. 2016 ; 123 124-129.[citado 2024 maio 07 ] Available from: https://doi.org/10.1016/j.sse.2016.05.004

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